Vias are routinely used in forming ICs. Vias may be formed that extend from the bottom of an IC die to one of the metal interconnect layers on the active or semiconductor top surface of the IC die. Such structures are often referred to as “through-silicon vias,” and are referred to more generally herein as through-substrate vias (TSVs).
TSVs are generally framed by a dielectric liner and are then filled with copper or another electrically conductive TSV filler material to provide a low resistance vertical electrical connection between the bottom of the IC die and the active circuitry on the semiconductor top surface of the IC die. The active circuitry formed on the semiconductor top surface comprises circuit elements that generally include transistors, diodes, capacitors, and resistors, as well as signal lines and other conductors that interconnect these various circuit elements.
A diffusion barrier metal formed on the dielectric liner frames the TSV and protects against escape of the TSV filler material to the semiconductor in the case of highly mobile metal TSV filler materials such as copper. Copper, as well as some other TSV filler metals, have a significantly higher coefficient of thermal expansion (CTE) as compared to silicon. For example, copper has a CTE of approximately 17 ppm/° C., whereas silicon has a CTE of approximately 2 to 3 ppm/° C. This CTE mismatch can result in significant thermally induced stress in the silicon and copper (or other conductive material filling the TSV via) during certain fab processing (e.g., 360 to 410° C. sinters) subsequent to the fabrication of the TSV, as well as during assembly and test/operation induced temperature stress, as may occur during solder reflow (e.g., up to about 260° C.), during certain temperature cycle (e.g., −55° C. to 125° C.) reliability testing, or even during long-term field operation of the IC.
In addition, when the TSVs are spaced relatively close together such that their stress fields interact, these stresses may be further magnified. The stresses that may result from the above-described CTE mismatch can lead to numerous problems, including interfacial delamination, cracking of the semiconductor material (e.g., silicon) or the dielectric above or lateral to the TSV, and/or degraded transistor performance.
To reach advanced processed nodes, lower dielectric constant (k) materials as compared to silica (k=3.9) have been used to reduce parasitic capacitance, enabling ICs to provide better performance, such as faster switching speeds and lower heat dissipation. As used herein a “low-k” dielectric has a k-value<3.4. “Ultra low-k” dielectrics are a subset of low-k materials. As used herein, ultra low-k dielectrics have a dielectric constant of less than 2.5. As known in the art, ultra low-k dielectrics tend to be significantly more brittle than conventional silica. Used in conjunction with TSVs, ultra low-k dielectrics (e.g. for inter-level dielectrics (ILDs)) are prone to cracking, particularly when the TSV filler metal (e.g., copper) has a CTE that is significantly different (and generally higher) as compared to the semiconductor (e.g., silicon). In the case of assembly based on thermo-compression bonding, mechanical stresses on the IC side of the TSV can be induced by thermo-compression bonding of the TSV tip, thus creating an opportunity for crack formation in the surrounding brittle low-k dielectric.
A number of solutions have been proposed to reduce problems caused by CTE mismatches for ICs having TSVs. Some solutions rely on TSV geometry or spacing. For example, one solution reduces the diameter of TSVs in order to reduce the stress from each TSV. This solution raises the TSV resistance. Another solution is to position the TSVs far apart from one another to limit the interaction of the stress fields between adjacent TSVs. A further solution is to position the TSVs far from any active circuitry to ensure stress fields do not penetrate the area proximate the active circuitry. Spacing solutions reduce packing density and can add resistance.
Some solutions rely on material substitutions. For example, tungsten (W) can be substituted for copper (Cu) to reduce the CTE mismatch with silicon. However, switching the TSV metal to W adds significant resistance (W has about 5× the resistance as compared to Cu) and can complicate processing since W does not generally allow direct electroplating.
Some other solutions rely on process changes. For example, the TSVs can be formed later in the process by etching through the entire back end of the line (BEOL) stack (multi-level metals and inter-level dielectrics (ILDs)) after BEOL processing thus avoiding putting the TSVs through the significant thermal cycling (e.g., 360 to 410° C. sinters) associated with BEOL processing. However, this approach blocks the ability to place routing channels (e.g., signal carrying) over the top of the TSVs since the TSVs in this process pass through all BEOL layers (i.e. including all metal interconnect levels). Moreover, as noted above, significant CTE induced stress can still occur from post BEOL processing, such as solder reflow during assembly.